TAS3108IADCPR TI
Available
TAS3108IADCPR TI
• 8 channel Programmable Audio Digital Signal • 16-, 20-, 24-, and 32-Bit Word Sizes Processor (DSP) • 64-fS, 128-fS, 192-fS, and 256-fS SCLK to • 135-MHz Maximum Speed, >2800 Processing Support Discrete 4 channel TDM, 6 channel Cycles Per Sample at 48 kHz TDM, and 8 channel TDM Data-Transfer Formats • Sample Rates of 32 kHz to 192 kHz • Two I 2 • 48-Bit Data Path and 28-Bit Coefficients C Ports for Slave or Master Download • Soft Volume Controller • Single-Cycle, 76-Bit Multiply Accumulate • Dither Generator • Five Simultaneous Operations Per Clock Cycle • Efficient log2 /2x Estimator • 1022 Words of 48-Bit Data Memory • Single 3.3-V Power Supply • 1022 Words of 28-Bit Coefficient Memory • 38-Pin Thin Shrink Small-Outline Package • 3K Words of 54-Bit Program RAM (TSSOP) (DCP) • 5.88K Words of 24-Bit Delay Memory • AEC-Q100 (Grade 2: –40°C to 105°C) (122.5 ms at 48 kHz) Compliant for Automotive Applications • 15 Stereo/TDM Data Formats (TAS3108IA) • Independent Input/Output Data Form
• 8 channel Programmable Audio Digital Signal • 16-, 20-, 24-, and 32-Bit Word Sizes Processor (DSP) • 64-fS, 128-fS, 192-fS, and 256-fS SCLK to • 135-MHz Maximum Speed, >2800 Processing Support Discrete 4 channel TDM, 6 channel Cycles Per Sample at 48 kHz TDM, and 8 channel TDM Data-Transfer Formats • Sample Rates of 32 kHz to 192 kHz • Two I 2 • 48-Bit Data Path and 28-Bit Coefficients C Ports for Slave or Master Download • Soft Volume Controller • Single-Cycle, 76-Bit Multiply Accumulate • Dither Generator • Five Simultaneous Operations Per Clock Cycle • Efficient log2 /2x Estimator • 1022 Words of 48-Bit Data Memory • Single 3.3-V Power Supply • 1022 Words of 28-Bit Coefficient Memory • 38-Pin Thin Shrink Small-Outline Package • 3K Words of 54-Bit Program RAM (TSSOP) (DCP) • 5.88K Words of 24-Bit Delay Memory • AEC-Q100 (Grade 2: –40°C to 105°C) (122.5 ms at 48 kHz) Compliant for Automotive Applications • 15 Stereo/TDM Data Formats (TAS3108IA) • Independent Input/Output Data Form
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